This application claims priority from Korean patent application No. 99-35679 filed Aug. 26, 1999 in the name of Samsung Electronics Co., Ltd., which is herein incorporated by reference.
1. Field of the Invention
The present invention relates generally to delay circuits, and more particularly, to delay circuits that provide high-resolution delay time control, and memory devices that utilize such delay circuits.
2. Description of the Related Art
Conventional delay circuits utilized a cascade of delayers, each having two serially connected inverters. When many delayers are connected in series, the overall time delay of the circuit is long. When some of the delayers are short circuited, the delay time decreases. However, the resolution of a conventional delay circuit can be no smaller than predetermined delay time of one of the delayers. Thus, it is impossible to provide precise control of the delay time.
When a prior art delay circuit as described above is adapted for use in a semiconductor memory device, it limits the speed at which the memory device can operate because the timing of internal control signals in a semiconductor memory device is an important factor for performing a high speed operation. For example, it is important to generate a precisely timed control signal to enable a sense amplifier to perceive a level difference of a pair of bit lines at the correct time. But as described above, a sense amplifier enable signal generator based on a conventional delay circuit which utilizes serially connected inverters for controlling an enable time cannot provide accurate enough control.
FIG. 1 is a circuit diagram of a prior art conventional delay circuit. The delay circuit comprises switches SW1, SW2, . . . , SW(n) and delayers D1, D2. . . , D(n+1), each of which includes two serially connected inverters(I1, I2), (I3, I4), . . . (I(2nxe2x88x921), I(2n)), and (I(2n+1), I(2n+2)). The delayers D1, D2, . . . D(n) are connected in parallel with the switches SW1, SW2, . . . SW(n), respectively. When the switches SW1, SW2, . . . SW(n) are turned on, the input signal IN is delayed as long as a delay time of delayer D(n+1). When the switches SW1, SW2, . . . SW(n) are turned off, the input signal IN is delayed as long as the delay time of all the delayers D1, D2, . . . D(n+1) combined. That is, the delay time of the input signal IN is maximized. When the switch SW1 is turned off and other switches SW2, SW3, . . . SW(n) are turned on, the input signal IN is delayed as long as the delay time of the delayers D1 and D(n+1).
Accordingly, with the delay circuit illustrated in FIG. 1, it is possible to increase or decrease the delay time by an amount equal to the delay time of one of the individual delayers. But, it is impossible to change the overall delay time by an amount of time that is smaller than the delay time of one of the individual delayers. This is especially problematic when trying to control the enable time of a sense amplifier enable signal generated by an sense amplifier enable signal generator in a semiconductor memory device.
One aspect of the present invention is a delay circuit comprising a slope controller for generating an intermediate signal responsive to an input signal, and a delay time controller coupled to the slope controller for generating an output signal responsive to the intermediate signal. The slope controller is constructed so as to control the slope of the intermediate signal responsive to one or more first select signals, and the delay time controller is constructed such that the delay time between an edge of the input signal and a corresponding edge of the output signal depends on the slope of the intermediate signal.
In another aspect of the present invention, a delay circuit comprises a slope controller for generating an intermediate signal responsive to an input signal, and a delay time controller coupled to the slope controller for generating an output signal responsive to the intermediate signal. The intermediate signal has a slope, and the delay time controller is constructed such that the delay time between the edge of the input signal and the corresponding edge of the output signal is responsive to one or more select signals.
Another aspect of the present invention is a delay circuit comprising slope controller means for generating an intermediate signal responsive to an input signal, and delay time controller means coupled to the slope controller for generating an output signal responsive to the intermediate signal. The delay time between an edge of the input signal and a corresponding edge of the output signal depends on the slope of the intermediate signal.